Method of fabricating a ferroelectric stacked memory cell

ABSTRACT

The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material and the same plate line. In this way, the manufacturing process is not critical and the size of the cells is minimal.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part of allowed U.S. patentapplication Ser. No. 09/911,637, filed Jul. 23, 2001, now pending, whichis a divisional of U.S. patent application Ser. No. 09/365,178, filedAug. 2, 1999, which issued as U.S. Pat. No. 6,300,650, both applicationsand the patent being incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention refers to a stacked type of memory cellstructure. In particular, the memory cell described is of theferroelectric non-volatile type, but the same structure can be used forDRAM cells.

[0004] 2. Description of the Related Art

[0005] As is known and shown in FIG. 1, a ferroelectric cell 1 iscomposed of a MOS transistor 2 and a capacitor 3 having, as adielectric, a ferroelectric material, for example PZT(PbZr_(1-x)Ti_(x)O₃, perovskite) or SBT (SrBi₂Ta₂O₉, layeredperovskite). In detail, in the ferroelectric cell 1, the NMOS-typetransistor 2 has a source terminal 4 connected to a bit line BL, a gateelectrode 5 connected to a word line WL and a drain terminal 6 connectedto a first plate 7 of the capacitor 3. A second plate 8 of the capacitor3 is connected to a plate line PL.

[0006] The cell is capable of storing binary information thanks to thehysteresis characteristics of the ferroelectric material which issandwiched between the plates 7 and 8 and which, when there are noapplied voltages, can assume two bias states depending on the sign ofpreviously-applied voltage across the capacitor 3 terminals.

[0007] All currently-known ferroelectric cells can be classified intotwo families: strapped cells and stacked cells.

[0008] In strapped cells, an embodiment of which is shown in FIG. 2, thecapacitor 3 is constructed above a field oxide region 10 that delimitsan active area 11 of the substrate 12 in which the conductive regions(source 13 and drain 14) of the transistor 2 are formed. In detail, thefirst plate 7 of the capacitor 3 is here placed on top and is made of asquare- or rectangular-shaped region of conductive material (forexample, platinum), connected to the drain region 14 of the transistor 2through a metallic connection line 16; the second plate 8 of thecapacitor 3 is here placed underneath and is made by a band ofconductive material (for example, platinum again) which runsperpendicular to the drawing plane and forms a plate line PL, connectedto other capacitors of adjacent cells; a dielectric region 17, offerroelectric material, is sandwiched between the first plate 7 and thesecond plate 8. The gate electrode 5 of the transistor 2 is made of aband of polycrystalline silicon which runs perpendicular to the drawingplane and forms a word line WL.

[0009] In stacked cells, an embodiment of which can be seen in FIG. 3,the capacitor 3 is constructed above the active area 11, directly abovethe drain region 14 of the transistor 2. In this case, the first plate 7of the capacitor 3 is placed underneath and is made by a square- orrectangular-shaped region of conductive material (for example, platinum)connected to the drain region 14 through a contact 23 formed in anopening of a protective layer 24 (for example BPSG) and the second plate8, of conductive material, is placed above and is connected to ametalization band 25 defining the plate line PL.

[0010] A titanium/titanium nitride region 26 runs below the first plate7 to help the adhesion of the first plate 7 of the capacitor 3 on theprotective layer 24.

[0011] The architecture of a array 28 of ferroelectric stacked orstrapped cells 1 is shown in FIG. 4. It will be noted that theferroelectric cells 1 are placed on rows and columns and are coupled sothat the cell pairs 27 are placed parallel to bit lines BL; thetransistors 2 of each cell pair 27 have common source regions, connectedto the same bit line BL; and the capacitors 3 belonging to the cellpairs 27 adjacent in a parallel direction to the bit lines BL areconnected to adjacent plate line pairs PL.

[0012] Ferroelectric stacked cells 1 are currently preferred, since theyare the only ones capable of meeting the scalability requirements of newCMOS technologies. In stacked cells, the layout rules on the capacitor 3design are crucial for the optimization of the cell.

SUMMARY OF THE INVENTION

[0013] There are therefore several known embodiments for stacked cells,apart from that shown in FIG. 3, in which both plates 7,8 and dielectricregion 17 are defined using a single mask and forming the plate line PLvia a special metallic band. For example, according to another knownarrangement, the first (lower) electrode 7 is formed by aseparately-shaped conductive region, while the dielectric region 17 andthe second (upper) electrode 8 are mutually aligned and shaped using asingle mask.

[0014] In all these cases, the connection of at least one of the plates7,8 with the same mask used for the connection of the ferroelectricmaterial composing the dielectric region 17 is critical; for example,during connection, slightly volatile components are formed, and thesecan be redeposited along the capacitor edge and damage its active zone,causing a decay in the ferroelectric properties of the capacitor, withan increase in edge losses and lower voltage strength.

[0015] On the other hand, the separate definition of the three partsconstituting the capacitor 3 (first and second plates 7,8 and dielectricregion 17), which would allow the problem presented by currentmanufacturing processes to be solved, causes an increase in overalldimensions that is in conflict with present trends towardsminiaturization. In fact, in making definition masks, account must betaken of both manufacturing tolerances (at present, with a 0.35 μmprocess, equal to 0.2 μm) and the minimum distances between the loweradjacent plates and the upper adjacent plates (for example, equal to 0.4μm). In particular, with the conditions given above, it would benecessary for the lower plate 7 to be wider, with respect to thedielectric region 7, by an amount at least equal to the manufacturingtolerance (at least 0.2 μm) on each side; similarly, it would benecessary for the dielectric region 17 to be wider, with respect to theupper plate 8, by the same amount; therefore, taking into account theminimum distance between the lower plates 7, the resulting overalldimensions for the capacitors 3 and consequently for the ferroelectriccells are excessive.

[0016] An object the present invention is making a stacked memory cell,without the described disadvantages. According to the present invention,a stacked memory cell is realized as claimed in claim 1.

[0017] In practice, according to the invention, the dielectric regionsof at least two adjacent cells in the direction of the bit lines are nolonger separate. In particular, the dielectric region 17 can becontinuous and shared between the two adjacent capacitors belonging topairs of adjacent cells. In this way, the layout definition rules forcapacitor scalability are given only by the distance between two loweradjacent electrodes and by the lateral space (enclosure) between upperelectrode and lower electrode. This allows, with the same cell area,maximizing the working area of the capacitor compared with the layout ofthe arrangement where three different masks for definition of thecapacitor are used and the dielectric region is divided between adjacentcells in the direction of the bit lines. This causes an increase insignal amplitude (proportional to the active area of the capacitor)supplied by each cell to the sense amplifier during reading.Alternatively, it is possible to obtain a reduction in the area occupiedby the ferroelectric cells.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] For a better understanding of the invention, an embodimentthereof will now be described, merely as a non-limiting example and withreference to the enclosed drawings, in which:

[0019]FIG. 1 shows the equivalent electrical diagram of a knownferroelectric cell.

[0020]FIG. 2 shows a cross-section through a first known type offerroelectric cell.

[0021]FIG. 3 shows a cross-section through a second known type offerroelectric cell.

[0022]FIG. 4 shows the known architecture of a memory cell array of thetype under consideration.

[0023]FIG. 5 shows a cross-section through a slice of semiconductormaterial in which cells have been constructed according to theinvention, taken along section line V-V in FIG. 7.

[0024]FIG. 6 shows a transverse section of ferroelectric cells accordingto the invention, taken along section line VI-VI in FIG. 5.

[0025]FIG. 7 shows the layout of two cells adjacent to each other,according to the invention.

[0026]FIG. 8 shows a cross-section through a slice of semiconductormaterial in which cells have been constructed according to a furtherembodiment of the invention, taken along section line VIII-VIII in FIG.9.

[0027]FIG. 9 shows the layout of two pairs of cells adjacent to eachother, according to the further embodiment of the invention.

[0028]FIG. 10 shows the architecture of a memory cell array comprisingcells according to the further embodiment of FIGS. 8 and 9.

DETAILED DESCRIPTION OF THE INVENTION

[0029] FIGS. 5-7 show stacked cells 1 constructed according to theinvention. The present description refers to ferroelectric cells inparticular, without being restricted to these.

[0030] In detail, FIG. 5 shows a pair of cells 27 and a singleferroelectric cell 1 adjacent to the pair of cells 27 in the directionof the bit lines (horizontal direction in FIG. 5). Pairs of adjacentcells 27 are insulated from each other by a thick oxide layer 30 (fieldoxide) which delimits, inside a P-type substrate 31, active areas 32 inwhich two drain regions 33 and a common N⁺ type source region 34 areformed. In a known way, gate electrodes 36 are formed above thesubstrate 31 and are insulated therefrom by a thin oxide layer 37. Thegate electrodes 36 are preferably made by bands comprising a doublelayer of polycrystalline silicon and tungsten silicide runningperpendicular to FIG. 5 and defining word lines; the gate electrodes 36are also laterally flanked by oxide spacers 38.

[0031] Less doped drain extension regions 39 are formed in the substrate31 below spacers 38 and a protective oxide layer 40 covers the surfaceof the substrate 31.

[0032] A first insulating layer 41 (for examples made of BoronPhosphorous Silicon Glass, or BPSG) runs above the protective oxidelayer 40 and has openings into which run first and second contacts 43,44 made of conductive material, for contacting the drain regions 33 and,respectively, the source regions 34.

[0033] Above the first insulating layer 41, there are formed lowerplates 50 (corresponding to the first plates 7 in FIG. 3) electricallyconnected to the first contacts 43; preferably, the lower plates 50 arecomposed of a lower portion 50 a made of titanium and an upper portion50 b made of platinum. Bands of ferroelectric material 51 run, withoutgaps, above and between adjacent pairs of lower plates 50, belonging todifferent pair of cells 27; in addition, the bands of ferroelectricmaterial 51 continuously run above and between the lower plates 50 ofadjacent cells in the cross section of FIG. 6, as also shown in thelayout of FIG. 7.

[0034] Above the bands of ferroelectric material 51, there are firstbands of conductive material 52 forming upper plates (corresponding tothe second plates 8 in FIG. 3) of the capacitors 3; the first bands ofconductive material 52 compose plate lines PL and, as is clear from FIG.7, have a smaller width compared to the lower plates 50.

[0035] Above the first insulating layer 41, there are also formed firstcontact regions 54, overlying and directly connected to the secondcontacts 44; the first contact regions 54 are also made preferably usinga double layer of titanium and platinum.

[0036] A second insulating layer 55 is formed above the first insulatinglayer 41, covering the first bands of conductive material 52; openingsare formed through the second insulating layer 55, into which thirdcontacts 56 run (FIG. 5), directly connected to the first contactregions 54, and openings into which fourth contacts 57 run (FIG. 6),directly connected to the first bands of conductive material 52. Abovethe second insulating layer 55 metalization lines 60 are formed thatdefine the bit lines BL and are directly connected to the third contacts56; in addition, second contact regions 61 are formed (FIG. 6) directlyconnected to the fourth contacts 57. The metalization lines 60 and thesecond contact regions 61 are formed in the first metalization level.

[0037] Above the second insulating layer 55, completely covering themetalization lines 60, there runs a third insulating layer 63, showingopenings into which fifth contacts 65 run (FIG. 6) directly connected tothe second contact regions 61; above the third insulating layer 63,third contact regions 66 are formed, directly connected to the fifthcontacts 65 and made in the second level of metalization, as well assecond bands of conductive material 67, connected, in a way not shown,to the word lines forming the gate electrodes 36.

[0038] A passivation layer 70 completely covers the device.

[0039] Purely by way of example, possible values relative to the regionswhich compose the ferroelectric cell 1 are given hereinbelow. The areaof the capacitor 2 is in the range between 1 and 5 m²; the lowertitanium portion 50 a of the lower plate is 20 nm thick; the upperplatinum portion 50 b has a thickness between 100 and 200 nm; the layerof ferroelectric material 51 has a thickness between 50 and 250 nm, andis preferably equal to 100 nm; the first bands of conductive material 52are approximately 200 nm thick.

[0040] The process for manufacturing the ferroelectric cells 1 shown inFIGS. 5-7 is as follows. After having made the transistors 2, havingcovered with the first insulating layer 41 and having made the first andsecond contacts 43, 44, in a way known per se, a layer of titanium andthen a layer of platinum are made (for example, by sputteringdeposition); the lower plates 50 are defined via a first mask(connection of platinum and titanium layers); a layer of ferroelectricmaterial is laid and then a layer of platinum is laid (for example, bysputtering deposition). Then, using a second mask, the first bands ofconductive material 52 (connection of platinum layer) are defined and,using a third mask, the bands of ferroelectric material 51 are defined.

[0041] The advantages that can be obtained with the present inventionare as follows. First of all, the ratio between capacitor 3 area andtotal cell 1 area is maximized. In fact, the restrictive rules in thecell design must now take into account only the distance between the twolower plates 50 belonging to adjacent pairs of cells 27 and theenclosure between the edges of the lower plate 50 and of the first bandof conductive material 52 of each cell.

[0042] In addition, critical points in the steps of photolithography andferroelectric material connection are removed.

[0043] Studies by the applicant have shown that the parasiticferroelectric capacitor formed between two capacitors 3 belonging to twopairs of adjacent cells 27 on the same row does not prejudice thecorrect operation of the ferroelectric cells 1, given the increasedthickness of the dielectric between the two plates 50 and the reducedfacing area of the two plates 50 themselves. In addition, the ratiobetween the active capacitance (capacitance of capacitors 3) and theparasitic capacitance improves with the reduction in thickness of thelower plate 50 and of the layer of ferroelectric material 51 andtherefore tends to be reduced with the increase in miniaturization ofthe devices, expected in the next technological generations.

[0044] Another embodiment is illustrated in FIGS. 8-10, where partsalready shown are indicated with the same reference numbers. In detail,FIG. 8 shows two pair of cells 127 arranged adjacent to each other inthe direction of the bit lines (horizontal direction in FIG. 8). Abovethe first insulating layer 41, there are the lower plates 50(corresponding to the first plates 7 in FIG. 3) of the capacitors 103,which are electrically connected to respective drain regions 33 in thesubstrate 31 through the first contacts 43. Bands of ferroelectricmaterial 51 run, without gaps, above and between adjacent pairs of lowerplates 50, belonging to different pair of cells 127; in addition, thebands of ferroelectric material 51 continuously run above and betweenthe lower plates 50 of adjacent cells in the cross section of FIG. 6, asalso shown in the layout of FIG. 7.

[0045] Bands of conductive material 152 extend above and in contact withthe bands of ferroelectric material 51; furthermore, the bands ofconductive material 152 and the bands of ferroelectric material 51 havethe same width and are aligned to each other. In detail, the bands ofconductive material 152 as well run, without gaps, above and betweenadjacent pairs of lower plates 50, belonging to different, adjacent pairof cells 127; in addition, the bands of conductive material 152continuously run above and between the lower plates 50 of adjacent cellsin a direction perpendicular to the bit lines 60, as also shown in thelayout of FIG. 9 (a cross section along a line corresponding to the lineVI-VI of FIG. 5 is identical to FIG. 6).

[0046] The bands of conductive material 152 form upper plates(corresponding to the second plates 8 in FIG. 3) of the capacitors 103and compose common plate lines PL as well. More precisely, the upperplates of adjacent capacitors 103 belonging to different pair of cells127 and the corresponding common plate line PL are made from the sameband of conductive material 152, which is thus shared therebetween.Hence, as also schematically shown in the electric diagram of FIG. 10,the upper plates of adjacent capacitors 103 belonging to different pairof cells 127 are connected to the same common plate line PL. Cellsbelonging to different pair of cells 127 and arranged adjacent to eachother in the direction of the bit lines 60 may be individually addressedthrough the respective word lines WL, which are still separated.

[0047] The process for manufacturing the ferroelectric cells shown inFIGS. 8-10 initially envisages the same steps as the process formanufacturing the ferroelectric cells 1. In particular, after havingmade the transistors 2, having covered with the first insulating layer41 and having made the first and second contacts 43, 44, in a way knownper se, a layer of titanium and then a layer of platinum are deposited(for example, by sputtering deposition); the lower plates 50 are definedvia a first mask (etch of platinum and titanium layers); a layer offerroelectric material is deposited and then a layer of platinum isdeposited (for example, by sputtering deposition). Then, both theplatinum layer and the ferroelectric layer are sequentially defined viaa single second mask, to form the bands of conductive material 152(plate lines) and the bands of ferroelectric material 51. Defining theconductive bands 152 and the ferroelectric bands 51 using a single maskensures that the bands 152, 51 are completely aligned with one another.That is, each conductive band 152 is coextensive with (i.e., has thesame length and width as), and directly on, a corresponding one of theferroelectric bands 51 to form the upper plates and ferroelectric layersof the capacitors 103 that are adjacent to each other in a firstdirection and a second direction perpendicular to the first direction.

[0048] The embodiment described with reference to FIGS. 8-10 has thefollowing advantages. First, the area of each capacitor is significantlyincreased without increasing the area of the cells. Moreover, themanufacturing process is simplified, since the band of ferroelectricmaterial and the upper plates of the capacitors are defined using asingle mask instead of two. Another important advantage of using asingle mask resides in that possible misalignments between the band offerroelectric material and the upper plates of the capacitors areprevented.

[0049] All of the above U.S. patents, U.S. patent applicationpublications, U.S. patent applications, foreign patents, foreign patentapplications and non-patent publications referred to in thisspecification and/or listed in the Application Data Sheet, areincorporated herein by reference, in their entirety.

[0050] Finally, it is evident that modifications and variations can bemade to the described cell, still remaining within the scope of thepresent invention.

[0051] For example, the layer of ferroelectric material 51 can run overthe whole surface of the first insulating layer 41 except for the zoneswhere the first contact regions 54 have to be made (openings 75 in FIG.5); the materials can differ from those described, as long as they aresuitable for the functions required; the exact arrangement of the areasand their dimensions can differ from those described above.

1. A process for manufacturing a memory array formed of a plurality ofstacked cells, comprising: making a plurality of MOS transistors inrespective active areas of a substrate made of semiconductor material,said step of making a plurality of MOS transistors comprising the stepsof making, for each one of said MOS transistors, a first and a secondconductive region in the substrate and a control electrode; forming aninsulating layer above the substrate; for each MOS transistor, formingfirst and second electrical contacts extending through the insulatinglayer, the first and second electrical contacts being positioneddirectly above and contacting the first and second conduction regions,respectively; making a plurality of capacitors, a corresponding one foreach one of said MOS transistors, above said active regions, said stepof making a plurality of capacitors comprising the steps of making, foreach one of said capacitors, a first plate directly above and in contactwith the first electrical contact of the corresponding MOS transistor, adielectric material region above said first plate, and a second plateabove said dielectric material region, each of the cells including oneof the MOS transistors and a corresponding one of the capacitors; makinga plurality of bit lines connected to said second conductive regions ofsaid MOS transistors by the second contacts; and making a plurality ofword lines and a plurality of plate lines running parallel to each otherand perpendicular to said bit lines, each word line being connected torespective control electrodes of said MOS transistors and each plateline being connected to respective second plates; wherein said step ofmaking a dielectric material region comprises the step of making a samedielectric region shared by two adjacent cells in a direction parallelto said bit lines, and said step of making second plates of thecapacitors comprises the step of making a same third conductive regionshared by the two adjacent cells in a direction parallel to said bitlines.
 2. The process according to claim 1, wherein making a pluralityof capacitors comprises: depositing a first conductive material layer;defining said first conductive material layer to form said first platesof said capacitors; depositing a dielectric material layer on said firstplates of said capacitors; depositing a second conductive material layeron said dielectric layer; sequentially etching said second conductivematerial layer and said dielectric material layer using a same mask, toform said same third conductive region and said same dielectric region,respectively.
 3. The process according to claim 2 wherein said samethird conductive region is aligned to said same dielectric region. 4.The process according to claim 2 wherein said same third conductiveregion has the same width as said same dielectric region, in saiddirection parallel to said bit lines.
 5. The process according to claim1, wherein said first plates of said capacitors form lower plates andsaid same dielectric region runs above and between the lower plates ofsaid two adjacent cells.
 6. The process according to claim 5, whereinsaid same dielectric region runs also on sides not facing each other ofsaid lower plates of said two adjacent cells.
 7. The process accordingto claim 1, further comprising forming a thick oxide layer thatseparates the MOS transistors of said two adjacent cells, wherein saidsame dielectric region and said same third conductive region run abovesaid thick oxide layer.
 8. The process according to claim 1, furthercomprising shaping said same dielectric region and said same thirdconductive region as respective elongated bands running perpendicular tosaid bit lines.
 9. The process according to claim 1 wherein said bitlines run above said capacitors, and said same dielectric region forms acontinuous layer except for openings corresponding to said contactregions.
 11. The process according to claim 1 wherein said dielectricmaterial region is made of ferroelectric material.
 12. A process forforming a memory array, comprising: forming a first stacked cell byforming a first transistor in a first active region of a semiconductivesubstrate and forming a first capacitor above the first active region,the first capacitor having a first and a second plate separated by afirst dielectric region; forming a second stacked cell by forming asecond transistor in a second active region of the substrate and forminga second capacitor above the second active region, the second capacitorhaving a first and a second plate separated by a second dielectricregion that is continuous with the first dielectric region, the secondplate of the second capacitor being continuous with the second plate ofthe first capacitor; and forming a third stacked cell by forming a thirdtransistor in a third active region of the substrate and forming a thirdcapacitor above the third active region, the third capacitor having afirst and a second plate separated from each other by a third dielectricregion that is continuous with the first and second dielectric regions,the second plate of the third capacitor being continuous with the secondplates of the first capacitor and the second capacitor, the first andsecond capacitors being positioned in a first directional line that istransverse to a second directional line in which the second and thirdcapacitors are positioned.
 13. The process of claim 12 wherein each ofthe first and second transistors includes first and second conductiveregions and a control region and the first plates of the first andsecond capacitors are coupled to the first conductive regions of thefirst and second transistors, respectively.
 14. The process of claim 12,wherein forming the first, second, and third capacitors includesdepositing a first layer of conductive material; defining said firstlayer of conductive material to form said first plates of saidcapacitors; depositing a layer of dielectric material above said firstplates; depositing a second layer of conductive material above saidlayer of dielectric material; defining said second layer of conductivematerial and said layer of dielectric material using a same mask to formsaid continuous second plates of said first, second, and thirdcapacitors and said continuous first, second, and third dielectricregions.
 15. The process of claim 12, wherein the second plates of thefirst, second and third transistors are part of a same plate lineextending along the second directional line, further comprising shapingthe first, second and third dielectric regions as a continuous elongatedband running in parallel to the plate line.
 16. The process of claim 12,further comprising forming a bit line connected to a conduction regionof one of the first and second transistors, the bit line extending abovethe first and second capacitors along the first directional line.
 17. Amemory array, comprising: a plurality of stacked cells, each cellincluding: a MOS transistor formed in an active region of a substrate ofsemiconductor material; a capacitor formed above said active region,each of said MOS transistors having a first and a second conductiveregion and a control electrode and each of said capacitors having afirst and a second plate separated by a dielectric material region; saidfirst conductive region of each of said MOS transistors being connectedto said first plate of a respective capacitor; a plurality of bit linesconnected to said second conductive regions of said MOS transistors ofrespective cells of the plurality of stacked cells; a plurality of wordlines connected to said control electrodes of respective said MOStransistors of the plurality of stacked cells; a plurality of platelines connected to said second plate of respective said capacitors, saidplate lines running perpendicular to said bit lines and parallel to saidword lines; wherein a pair of cells adjacent to each other in adirection parallel to said bit lines share a same dielectric materialregion and a same third conductive region, forming said second plates ofsaid capacitors of said pair of cells.
 18. The memory array according toclaim 17, wherein said first plates of said capacitors form lower platesand said same dielectric material region runs above and between thelower plates of said two adjacent cells.
 19. The memory array accordingto claim 18, wherein said same dielectric material region runs also onsides not facing each other of said lower plates of said two adjacentcells.
 20. The memory array according to claim 17, wherein said samedielectric material region is shaped as a band running in parallel tosaid respective plate line.
 21. The memory array according to claim 17,wherein said same third conductive region is positioned on andcoextensive with said same dielectric region.
 22. The memory arrayaccording to claim 21, wherein said same third conductive region has thesame width as said same dielectric region, in said direction parallel tosaid bit lines.
 23. The memory array according to claim 17, wherein saiddielectric material region is made of ferroelectric material.
 24. Amemory array, comprising: a substrate of semiconductor material; a firststacked cell comprising a first transistor formed in a first activeregion of the substrate and a first capacitor formed above the firstactive region, the first capacitor having a first and a second plateseparated by a first dielectric region; a second stacked cell comprisinga second transistor formed in a second active region of the substrateand a second capacitor formed above the second active region, the secondcapacitor having a first and a second plate separated by a seconddielectric region that is continuous with the first dielectric region,the second plate of the second capacitor being continuous with thesecond plate of the first capacitor; and a third stacked cell comprisinga third transistor formed in a third active region of the substrate anda third capacitor formed above the third active region, the thirdcapacitor having a first and a second plate separated from each other bya third dielectric region that is continuous with the first and seconddielectric regions, the second plate of the third capacitor beingcontinuous with the second plates of the first capacitor and the secondcapacitor, the first and second capacitors being positioned in a firstplane that is transverse to a second plane in which the second and thirdcapacitors are positioned.
 25. The memory array according to claim 24,wherein said first plates of said capacitors form lower plates and saiddielectric regions are part of a dielectric layer that runs above andbetween the lower plates of said capacitors.
 26. The memory arrayaccording to claim 25, wherein said dielectric layer runs also on sidesnot facing each other of said lower plates of said capacitors.
 27. Thememory array according to claim 24, wherein said dielectric regions arepart of a dielectric layer that is shaped as a dielectric band extendingin a first direction and the second plates are part of a plate lineextending in the first direction in parallel to said dielectric band.28. The memory array according to claim 24, wherein said conductive bandis positioned on and coextensive with said dielectric band.
 29. Thememory array according to claim 24, wherein said dielectric regions aremade of ferroelectric material.